Adaptive equalization methods and apparatus

ABSTRACT

A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e.g., equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.

BACKGROUND OF THE INVENTION

This invention relates to digital data communication, and moreparticularly to methods and apparatus for automatically adjusting thecircuitry involved in such communication to compensate for losses in adigital data signal transmitted from transmitter circuitry to receivercircuitry.

Different signal transmission media tend to have different signaltransmission characteristics. For example, a cable may have a differenttransmission characteristic than a printed circuit board backplane. Inaddition, each instance of any given type of transmission medium mayhave somewhat different characteristics, within a range that is typicalfor that type of transmission medium. It is also possible for atransmission medium to change over time or as a result of otherenvironmental factors.

Among the characteristics that can adversely affect the performance of atransmission medium are attenuation and phase shift. It is common forthe amount of attenuation and phase shift to be frequency-dependent.Typically, both attenuation and phase shift tend to increase withincreasing frequency. For convenience herein, attenuation, phase shift,and other forms of signal degradation are sometimes referred togenerically as “losses.”

In order to have satisfactory transmission of a digital data signal,especially at high data rates or high frequencies, it may be necessaryto compensate for losses in the signal being transmitted. Moreover,because such losses can vary from instance to instance and from time totime, it can be desirable for such compensation to be at least partlyautomatic or adaptive. A term that is often used for such compensationis equalization. The term pre-emphasis is also sometimes used forcompensation or equalization that is performed at the transmitter, i.e.,anticipating losses that will occur and compensating for them bymodifying the signal before it is transmitted. When the termpre-emphasis is used, equalization may then be used as the term forcompensation performed at the receiver. The present inventors tend toprefer equalization performed at the receiver, but aspects of thisinvention may also be applied to equalization (pre-emphasis) performedat the transmitter.

Programmable circuitry such as programmable logic device (“PLD”)circuitry has capabilities that can be useful in supporting adaptiveequalization. For example, a PLD or PLD circuitry may be one of thecomponents involved in transmitting or receiving a signal needingadaptive equalization, or such circuitry may be used for controllingcertain aspects of the circuitry that transmits and/or receives such asignal. Such programmable circuitry (e.g., PLD circuitry) can beespecially useful in implementations of this invention becauseprogrammability aids in providing different parameters and/or proceduresfor addressing different transmission loss characteristics that may beencountered.

SUMMARY OF THE INVENTION

A system in accordance with the invention typically includes aprogrammable transmitter device (e.g., a PLD) connected to aprogrammable receiver device (e.g., another PLD) via a transmissionmedium (e.g., a printed circuit board backplane or a cable) fortransmitting a high-speed data signal from the transmitter to thereceiver. A low-speed communication link is also provided between thetransmitter and the receiver. During a test mode of operation, thetransmitter and receiver communicate with one another via the low-speedlink to cause the transmitter to transmit test signals having knowncharacteristics via the high-speed transmission medium. For example,these test signals may have known amplitude and successively differentfrequencies. The receiver analyzes the test signals as received. Forexample, the receiver may subject each test signal (having a particularfrequency) to a series of different amplitude tests (using a series ofdifferent amplitude threshold levels) to determine the approximateamplitude of each test signal frequency as received by the receiver. Theresulting amplitude vs. frequency information can be used in any ofseveral ways to determine what steps should be taken to at least partlycompensate for any signal losses that have been detected. For example,an approximate transfer function can be deduced from this amplitude vs.frequency information. That transfer function (and/or the amplitude vs.frequency information itself) can be used to calculate one or morecompensation-control parameters that, when used in the transmitterand/or receiver circuitry, should allow the system to at least partlycompensate for losses of the kind that have been detected. As anotherexample, the amplitude vs. frequency information may be compared toseveral reference sets of such information to find the most nearlymatching reference set. One or more compensation-control parametersstored in association with the most nearly matching reference set areretrieved to control the provision of compensation for losses of thekind detected. However they are determined, use of thecompensation-control parameter(s) preferably includes at least controlof one or more aspects of equalizer circuit components of the receiver.It may also include control of one or more aspects of the transmitter(e.g., pre-emphasis capability of the transmitter).

After initial compensation measures have been taken, the effectivenessof those measures may be determined by transmitting further test signalsvia the high-speed transmission medium. These further test signals mayinclude any or all of (1) more test signals like those used initiallyand described above, (2) a data signal having a known data eye width,and/or (3) a known data signal. Further test signals (1) above can besubjected to analysis similar to at least a portion of the analysisdescribed earlier. Further test signals (2) above can be subjected to areceived data eye width measurement. Further test signals (3) above canbe subjected to a bit error rate (“BER”) analysis. If any of thesefurther tests indicate that the compensation measures already taken arenot appropriately effective, compensation can be further adjusted.

Further features of the invention, its nature and various advantages,will be more apparent from the accompanying drawings and the followingdetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified, schematic block diagram of an illustrativesystem that can be constructed and operated in accordance with theinvention.

FIG. 2 shows an equation that is useful in explaining certain aspects ofthe invention.

FIG. 3 is an illustrative transfer function graph that is useful inexplaining certain aspects of the invention.

FIGS. 4 a and 4 b are collectively a simplified flow chart ofillustrative operations in accordance with the invention.

FIG. 5 is a table showing illustrative information about systemperformance that may be collected and tabulated in accordance with theinvention.

FIGS. 6 a and 6 b are collectively a simplified flow chart of possiblefurther illustrative operations in accordance with the invention.

FIG. 7 is another table showing further illustrative information aboutsystem performance that may be collected in accordance with theinvention.

FIG. 8 is similar to a portion of FIG. 1, with possible additionalillustrative components in accordance with the invention.

FIG. 9 is another simplified flow chart of still further possibleoperations in accordance with the invention.

FIG. 10 is yet another simplified flow chart of still more possibleoperations in accordance with the invention.

DETAILED DESCRIPTION

An illustrative system 10 that can be constructed in accordance with theinvention is shown in FIG. 1. System 10 includes two PLDs 20 and 40.Although the term “PLD” is used for devices 20 and 40, it will beunderstood that these devices can be any of various device types havingthe capabilities needed to implement this invention. The requiredcapabilities of devices 20 and 40 will become fully apparent as thisspecification proceeds. Although devices 20 and 40 thus need to have thecapabilities needed to implement this invention, they may also haveother capabilities needed to perform other functions. Also, althoughdevice 20 is shown primarily as a data transmitter in FIG. 1, andalthough device 40 is shown primarily as a data receiver in the FIG., itwill be understood that each of these devices may also include thecapabilities depicted for the other, so that either or both may act asboth a transmitter and a receiver. Any such transmitter/receiver mayexchange data bi-directionally with another transmitter/receiver. Or thetransmitter portion may transmit data to one other device and receivedata from a second other device.

System 10 also includes a transmission medium 30 by which data istransmitted from device 20 to device 40. Transmission medium 30 is shownin FIG. 1 as a backplane, cable, or other similar communication medium.Devices 20 and 40 may be manufactured without full knowledge of orcontrol over the transmission characteristics of medium 30. Medium 30may also be subject to some variation in transmission characteristics(e.g., due manufacturing process variation, age, or environmentalchanges). Devices 20 and 40 are therefore provided, in accordance withthis invention, with the ability to automatically (or substantiallyautomatically) modify aspects of their own performance (or at leastaspects of the performance of one of devices 20 or 40) to compensate forpossible deficiencies or inefficiencies of medium 30 in transmittingdata.

Device 20 is shown in FIG. 1 as including control element 22 anddifferential output driver 24. Control element 22 includes the abilityto output a data signal having a variety of characteristics. Forexample, in order to effectively synthesize a signal having any of awide range of frequencies, control element 22 may be able to output adata signal having any number of data 1 bits alternating with any numberof data 0 bits. (For convenience herein it will be assumed that a data 1bit is represented by a relatively high voltage level, and that a data 0bit is represented by a relatively low voltage level. But thisconvention can be reversed if desired.) A data signal having alternating1s and 0s has the highest possible frequency; a data signal having two1s alternating with two 0s has half the highest frequency; a data signalhaving three is alternating with three 0s has one-third the highestfrequency; and so on. Other examples of data signals that controlelement 22 may be able to output include (1) predetermined test datasequences and (2) actual data (e.g., from some other source 26 on device20). Control element 22 may also be able to vary the output voltage(“Vod”) of the data signal output by device 20. Still another possiblecapability of control element 22 may be the ability to give the dataoutput signal “pre-emphasis,” especially a controllable amount ofpre-emphasis. Pre-emphasis is some extra energy (e.g., some extravoltage change) immediately adjacent to (but following) each transitionin the level of the data signal. The respect(s) in which element 22 maycontrol pre-emphasis may include (1) the amount of extra voltage changegiven the data signal adjacently following each transition in thatsignal, (2) the duration of that extra voltage change, (3) the shape ofthe extra voltage change, and/or (4) de-emphasizing non-transitioningbits in the data signal. (Although controlling voltage is referred toprimarily herein in connection with pre-emphasis, it will be understoodthat controlling energy or current are among the possible alternatives.)

Output driver 24 converts a single-ended data signal output by controlelement 22 to a pair of differential output signals applied totransmission medium 30. Although differential data signalling betweendevices 20 and 40 is shown in FIG. 1, this is only an example, andsingle-ended (i.e., non-differential) signalling could be used insteadif desired. Another point that should be mentioned here is that althoughFIG. 1 shows elements 22 and 24 as separate from one another, element 24may be wholly or partly integrated into element 22, and some of thecontrol described above in connection with element 22 may be effectedusing components of element 24.

Device 40 is shown in FIG. 1 as including differential input driver 42,equalizer circuitry 44, peak detector circuitry 46, processor circuitry50, and memory circuitry 60.

Input driver 42 applies the differential data signal received fromdevice 20 via transmission medium 30 to equalizer 44. Equalizer 44 iscontrollable by processor 50 to give the output signals of driver 42 acontrollable amount of extra energy (e.g., extra voltage change)immediately adjacent to (but following) each transition in the datasignal output by driver 42 and/or to perform any other signalconditioning that is covered by the general term equalization. Forexample (and as in the case of pre-emphasis), equalizer 44 may controlsuch aspects as the amount, duration, and/or shape of the extra energyimparted after each data signal transition. Also as in the case ofpre-emphasis, voltage control is primarily referred to herein inconnection with equalization. But energy or current control are possiblealternatives. Although elements 42 and 44 are shown as separate in FIG.1, it will be understood that they may be wholly or partly combined, sothat some of the control described above in connection with equalizer 44may be performed by components of input driver 42.

An amplitude-indicating output signal of equalizer 44 is applied to peakdetector 46. (Other output signals 48 of equalizer 44 are applied toother circuitry (e.g., as in FIG. 8) for recovery from those signals ofthe received data. In FIG. 8, for example, the recovered data signal ison line 312, which may include a connection 314 for routing that signalto the programmable logic and/or other circuitry of PLD 40.) Peakdetector 46 is essentially an analog-to-digital converter which treatsthe output signal of equalizer 44 that it receives like an analog signalthat needs to be converted to a digital signal based on whether thelevel of the equalizer output signal is above or below a threshold level(“Vid”). The threshold level used by peak detector 46 may be variableand controlled by processor 50.

The output signal of peak detector 46 is applied to processor 50. Inaddition to making use of the output signal of peak detector 46,processor 50 may make use of information it retrieves from memory 60.Processor 50 can send signals to device 20 via communication link 70 forcontrolling or partly controlling operation of control element 22.Communication link 70 can be a relatively low-speed link for whichsignal attenuation (typically greater at higher frequencies) is not aproblem.

A typical, generalized transmission characteristic (“transfer function”)of transmission medium 30 may be given by the equation shown in FIG. 2.In this equation “S21” is the ratio of energy out of medium 30 to energyinto that medium, “f” is frequency, and “a1-a3” are coefficients thatcan vary from system to system, and even from time to time for any givensystem based on such factors as system age and/or environmentalconditions. A typical, generalized graph of the transfer function ofFIG. 2 is shown in FIG. 3. (The horizontal axis is FIG. 3 is labelledwith two different frequency ranges illustrating two different possibleexamples. Many other examples are also possible.) It will be understoodthat FIG. 3 is only illustrative, and that a curve like that shown inFIG. 3 can be shifted left or right, can have steeper or shallowerdrop-off, etc., depending on the parameters a1-a3 of any particularsystem. It will also be understood that the generalized characteristicsrepresented by FIGS. 2 and 3 are only examples, and that a system may begoverned by a different type of transfer function, which when graphedproduces a curve having a different type of shape than the curve shownin FIG. 3. A very common characteristic of transmission media likemedium 30, however, is that they behave like a low pass filter to afirst order of approximation. This means that low frequency signalcomponents pass with little or no attenuation, while higher frequencysignal components experience more attenuation. The present inventionallows system 10 to compensate for whatever losses transmission medium30 is imposing on the data signal being transmitted from device 20 todevice 40.

In order to determine and implement the appropriate compensation fortransmission losses, system 10 may be operated as shown in FIGS. 4 a and4 b. In step 110 processor 50 (FIG. 1) sets the value of Vod used bycontrol element 22. For example, processor 50 may cause element 22 touse a Vod of 900 mV.

In step 112 processor 50 causes control 22 to output a succession oftest signals that simulate waveforms having different frequencies. Thiscan be done by having control 22 output a data signal having differentnumbers of alternating 0s and 0s. The table below shows examples of thisfor an illustrative system having a maximum data rate of 3.2 Gbps(gigabits per second).

Number of Simulated Repeating 1s and 0s Frequency (MHz) 1 (i.e., 101010. . . ) 1600  2 (i.e., 11001100 . . . ) 800 3 533.333 . . . 4 400 5 3206 266.666 . . . 7 228.571 . . . 8 200 9 177.777 . . . 10 160 20  80 30 53.333 . . . 40  40 50  32Each simulated frequency is transmitted long enough to permit step 116to be performed for that frequency. Then a different frequency istransmitted. Collectively the different frequencies used span at least asignificant portion of the frequency spectrum in which actual data to betransmitted will lie.

In step 114, during the transmission of each simulated frequency,processor 50 causes the threshold level used by peak detector 46 tochange until it is possible to discriminate between a threshold that isjust below the high (peak) voltage in the signal output by equalizer 44and a threshold that is just above that high (peak) voltage.

In step 116 the results of step 114 are tabulated, e.g., as shown inFIG. 5. Processor 50 may perform this tabulation, possibly using memory60 to store the results. In FIG. 5 a Y (for yes) entry means that thepeak voltage output by equalizer 44 is greater than the thresholdvoltage setting shown at the horizontally aligned point in the left-mostcolumn in the FIG. In FIG. 5 an N (for no) entry means that the peakvoltage output by equalizer 44 is not as high as the threshold voltagesetting shown at the horizontally aligned point in the left-most column.Thus the values in the left-most column in FIG. 5 are illustrative ofthe different threshold voltage settings peak detector 46 can becontrolled to employ during the output of each different frequency bycontrol 22. In the particular example shown in FIG. 5 the frequenciesoutput by control 22 are 32 MHz, 80 MHz, 200 MHz, 320 MHz, 400 MHz, 800MHz, and 1600 MHz. (It may not be necessary to try every possiblethreshold value shown in the left-hand column in FIG. 5. For example,assuming that progressively greater threshold values are employed duringthe transmission of each frequency, once one or two threshold valueshave been reached that produce an N result, it can probably be safelyassumed that all higher threshold values will also produce N resultswithout taking the time to actually try those higher threshold values.)The line plotted through the highest Y values in the various columns inFIG. 5 is somewhat similar to the theoretical curve shown in FIG. 3. Forexample, both FIG. 3 and FIG. 5 show transfer functions that are downabout 6 dB at 1.6 GHz. In particular, in the case of FIG. 5 the receiversees about 800 mV of Vid at low frequencies (e.g., 32 MHz). But at 1.6GHz the receiver sees about 400 mV of Vid. This is an attenuation factorof about −6 dB.

Once a transfer function characteristic has been determined as in step116, step 120 (FIG. 4 b) is performed to determine compensation settingsthat are appropriate for counteracting the attenuation characteristicthat has been found. (For the moment it will be assumed that thecompensation settings determined in step 120 are the final compensationsettings. Later it will be explained that the step 120 settings may beonly initial settings, with additional optional steps 130 beingsubsequently employed to possibly refine the initial settings.)

Step 120 may be performed based on either empirical data orcalculations. In either case, processor 50 may perform the analysis. Ifstep 120 is performed on the basis of empirical data, data for severaldifferent possible transfer functions may have been previously stored inmemory 60 in association with compensation settings that are appropriatefor counteracting the attenuation characteristics of each transferfunction. In step 120 processor 50 finds the stored empirical data setthat best matches the data collected from the performance of steps110-116, and the processor retrieves from memory the compensationsettings stored in association with that empirical data set. In step 122processor implements those compensation settings. For example, in step120 processor 50 may look for the empirical data set havingapproximately the same roll-off characteristics at a desired data rate.The associated compensation settings that are retrieved from memory 60as part of step 120 and then implemented in step 122 may include one ormore of the following: (1) a pre-emphasis setting for control 22, (2) anequalization setting for equalizer 44, and/or (3) a Vod setting forcontrol 22. The presently most preferred embodiments use at leastcontrol of equalizer 44 (item 2 in the preceding sentence). Heavyreliance on pre-emphasis (item 1 above) may have the disadvantage ofincreasing crosstalk between adjacent communication channels like 30.High Vod (item 3 above) may have a similar disadvantage, and also tendsto increase power consumption.

As an alternative to reliance on empirical data, processor 50 mayperform step 120 by performing one or more calculations. As just oneexample of such possible calculations, processor 50 may calculate asetting for the first post tap of pre-emphasis (in control 22) and/orequalization (in equalizer 44) by trying to compensate for the amount ofattenuation measured in FIG. 5. Processor 50 can calculate thesetting(s) needed to best compensate the attenuation measured in FIG. 5.Again, the presently most preferred embodiments use at least control ofequalizer 44, because heavy reliance on pre-emphasis may have thedisadvantage of increasing crosstalk between adjacent channels 30.

After step 122 has been performed, and assuming that optional steps 130(described later) are not performed, transmission of actual data canbegin as shown by step 140.

One or more of several optional steps 130 may be performed between steps122 and 140. These optional steps may be for such purposes as furtherrefining the compensation settings initially implemented in step 122and/or testing to make sure that data is being received withsatisfactory reliability.

An illustrative step 130 for possibly refining compensation settingsinitially implemented in step 122 is shown in more detail in FIGS. 6 aand 6 b. In step 210 any initial compensation settings that have beenimplemented in step 122 are turned off by processor 50. In step 212processor 50 causes control 22 to transmit a relatively low frequencysignal (e.g., a 32 MHz signal as shown in the second column of FIG. 7).In step 214 processor 50 causes the threshold level of peak detector 46to change gradually until it is possible to discriminate between thehighest threshold value that allows a high level in the output signal ofequalizer 44 to pass and the lowest threshold value that does not allowsuch a high level to pass. In the particular example illustrated by thefirst two columns in FIG. 7, with Vod set at 800 mV, the highest Vidthat allows a data high from equalizer 44 to pass should be 800 mV (thisis the highest Y in the second column in FIG. 7). The lowest Vid thatdoes not allow a data high from equalizer 44 to pass is 900 mV (this isthe lowest N in the second column in FIG. 7). A relatively low frequencysignal (e.g., 32 MHz) is used for this series of steps becauseattenuation should be relatively small at low frequencies.

It may not be necessary to perform steps 210-214 if data like that shownin the second column of FIG. 7 is available from performance of steps112-116 with a suitably low frequency signal.

Continuing with FIG. 6 a, in step 220 the compensation settingsdetermined in step 120 are implemented by processor 50. Then in step 230processor 50 causes elements 22 and 24 to transmit a high frequency(e.g., a 1600 MHz signal as in the third column of FIG. 7). Step 232 islike step 214, but for the high frequency signal. In step 240 processor50 compares the “trip point” (transition from Y to N) in the thirdcolumn in FIG. 7 to the “trip point” in the second column in FIG. 7. Ifthe high frequency trip point is higher than the low frequency trippoint, step 242 is performed by processor 50 to somewhat decrease thecompensation implemented. Control then returns to step 230 for anotherpass from that step onward. If in step 240 the high frequency trip pointis lower than the low frequency trip point, then step 244 is performedby processor 50 to somewhat increase the compensation implemented.Control then returns to step 230 for another pass from that step onward.If in step 240 the high frequency trip point is about equal to the lowfrequency trip point, then convergence has been reached and step 246 isperformed to exit from this sequence of steps.

The four right-hand columns in FIG. 7 show data from four illustrativepasses through steps 230 et seq. in FIGS. 6 a and 6 b. In the third fromleft column the compensation is initially too little (because thetransition from Y to N in the third from left column is lower than thetransition from Y to N in the second from left column). The initialcompensation is accordingly increased. However, the fourth from leftcolumn in FIG. 7 shows that the increase has been too great (because nowthe transition from Y to N is higher than in the second from leftcolumn). The compensation is therefore lowered somewhat. Again, however,it is found that the compensation is too low (because the transitionfrom Y to N in the fifth from left column is lower than in the secondfrom left column). The compensation is therefore increased again. Inthis way compensation settings are eventually reached (as in theright-most column in FIG. 7) that make the Y to N transition for thehigh frequency signal approximately equal to that for the low frequencysignal.

The degree of precision that can be achieved in accordance with FIGS. 6a, 6 b, and 7 may depend to some extent on how closely spaced theavailable signal detector thresholds are (left-hand column in FIG. 9).More closely spaced signal detector thresholds should increaseachievable precision.

Another example of an optional step 130 (FIG. 4 b) that can be used torefine compensation settings in accordance with the invention is to testthe width of the data eye in a compensated data signal. The data eye isthe time between the most closely spaced transitions in a data signal.If the received data eye becomes too small (as compared to what it wasat the transmitter), errors may occur in interpreting the received databecause it may become difficult or impossible to always sample thereceived data at points that are sufficiently spaced from transitions toavoid erroneous sampling results.

Illustrative capability that may be included in PLD 40 to determine thewidth of the data eye is shown in FIG. 8. In addition to elementsalready shown in FIG. 1 and described above, FIG. 8 shows slicercircuitry 310 for sampling the output signals 48 of equalizer 44 attimes determined by a clock-type output signal of clock-type circuitry320. The phase of the output signal of circuitry 320 is controllable byprocessor 50. During operation of the components shown in FIG. 8, knowntest data is transmitted by transmitter 20 (FIG. 1) to receiver 40 viatransmission medium 30. Transmitter 20 may be controlled to do this byprocessor 50 sending appropriate control signals to control 22 viacommunication link 70. Although the known test data may have any of anumber characteristics, one desirable characteristic that it may have isthe appearance of randomness (although it is in fact fully specified andtherefore known prior to transmission). An exact replica of the knowntest data may be stored in memory 60 as shown in FIG. 8.

As transmitter 20 transmits the test data, slicer 310 attempts torecover it using a clock signal phase from circuitry 320 determined byprocessor 50. Comparator circuitry 330 compares the serial data signal312 output by slicer 310 to the replica of the test data concurrentlyand synchronously output by memory 60. Any bits that comparator 330receives that do not match one another indicate that slicer 310 is notsampling the received data signal at the time required to correctlycapture a bit in that signal. Processor 50 periodically changes thephase employed by circuitry 320 in small increments. Accordingly, afterenough of these incremental changes to the phase of circuitry 320 havebeen made, the sampling time of slicer 310 will have been effectivelyswept across the received data eye. The number of phase increments forwhich data capture remains error-free (or substantially error-free) is ameasure of the width of the received data eye. If processor 50 findsthat the received data eye is too narrow (e.g., as compared to the knowndata eye at transmitter 20), processor 50 can adjust the compensationsettings (e.g., from step 122 in FIG. 4 b) to widen the received dataeye.

Illustrative steps for using capability of the type shown in FIG. 8 areshown in FIG. 9. Step 410 describes using different phases output bycircuitry 320 in FIG. 8 to sample the received data at different times.(An alternative would be to introduce different amounts of delay intothe received data signal going into slicer circuitry 310.) Step 420describes detecting whether or not each phase used in step 410 givesmore than a threshold number of data errors. (An alternative to “on thefly” comparison between two serial signals (as in comparator 330 in FIG.8) would be to accumulate the received serial data output by slicer 310in another part of memory 60 and then later compare that received datato the expected data.)

If a first performance of steps 410 and 420 does not indicate that thereceived data signal has an eye of acceptable width, then step 430 isperformed to repeat steps 410 and 420 with another set of compensationsettings that it may be desired to test. Step 430 can be repeated asmany times as desired. Then step 440 is performed to pick thecompensation settings that gave the best results from the variousperformances of step 430.

From the foregoing it will be seen that FIG. 9 is another illustrativeembodiment of what is described as optional step(s) 130 in FIG. 4 b.FIG. 8 is an illustrative embodiment of circuit capability for carryingout the FIG. 9 steps. The various embodiments of optional step(s) 130 inFIG. 4 b shown and described herein can be used individually or in anycombination, or omitted entirely, as desired.

Still another example of an optional step 130 (FIG. 4 b) in accordancewith the invention is to test whether the bit error rate (“BER”) isacceptable. This may be done, for example, as shown in FIG. 10. In step510 processor 50 (FIG. 1) sets up a bit error rate test betweentransmitter 20 and receiver 40. For example, processor 50 may selectsuch parameters as the bit error rate that is acceptable (e.g., no morethan 1 error in 10¹² bits), the test data to be used, the time durationof the test, etc. In step 520 processor 50 may initiate the BER test(e.g., by commanding control 22 to begin to send the BER test data).Also in step 520 processor 50 may keep track of the results as the testproceeds. For example, processor 50 may use an arrangement ofcapabilities like those represented by elements 60 and 330 in FIG. 8 tocompare received serial data to the expected data output by memory 60and to keep track of any discrepancies (errors) detected by thatcomparison.

At the conclusion of the BER test, step 530 is performed to determinewhether the test results were satisfactory (i.e., whether or not the biterror rate was acceptably low). If so, control passes to step 540 toexit from this series of steps without need for any change in previouslyestablished compensation settings. If not, step 550 may be performed totry some further adjustment to the compensation settings. For example,if the optional steps illustrated by FIGS. 8 and 9 were not previouslyemployed, then step 550 could cause those steps to now be tried. Asanother example, if step 120 (FIG. 4 b) was first performed usingcalculations, then step 120 might be performed again based on empiricaldata (followed by re-performance of the steps following step 120).

It will be understood that the foregoing is only illustrative of theprinciples of the invention, and that various modifications can be madeby those skilled in the art without departing from the scope and spiritof the invention. For example, although processor 50 is shown inreceiver PLD 40, some or all of that component could instead be intransmitter PLD 20, with communication via link 70 being bi-directionalor reversed from the direction shown in FIG. 1. By using programmable(configurable) components such as PLDs 20 and 40, any of a wide range ofdifferent compensation algorithms can be implemented. Moreover, theparticular parameter values used in these parameters can also be varied.Similarly, the particular signal handling that is performed to effectdesired compensation can vary over a wide range. Some examples of thingscan be done to effect compensation are the various aspects ofequalization control that are shown and described in Wong et al. U.S.patent application Ser. No. 10/762,864, filed Jan. 21, 2004.

1. A method of controlling compensation for loss in transmission of adata signal from transmitter circuitry to receiver circuitry comprising:transmitting a plurality of test signals in succession having knownamplitudes and respective different frequencies; measuring amplitude ofeach test signal as received by the receiver; storing a plurality ofvalues, for each test signal, indicative of whether the measuredamplitude of the test signal is greater than or less than apredetermined threshold value; receiving a feedback signal from thereceiver circuitry to adjust the predetermined threshold value when themeasured amplitude of the test signal is less than the predeterminedthreshold value; and after the amplitude of each of the plurality oftest signals is measured: analyzing the stored plurality of values foreach test signal to identify at least one frequency where thepredetermined threshold value has been adjusted to determine thatunacceptable loss is occurring for the corresponding test signal;generating a transfer function based on the stored plurality of valuesfor each test signal in response to identification of the test signalwith the frequency at which unacceptable loss is occurring; anddetermining compensation based on the generated transfer function thatwill at least partly reduce the unacceptable loss.
 2. The method definedin claim 1 wherein the measuring comprises: using a plurality ofdifferent amplitude thresholds to find a threshold that is close to theamplitude of the test signal as received by the receiver.
 3. The methoddefined in claim 1 further comprising: tabulating results of pluralperformances of the measuring to produce transfer function information.4. The method defined in claim 3 further comprising: using the transferfunction information to calculate at least one parameter for use incontrolling compensation circuitry.
 5. The method defined in claim 3further comprising: comparing the transfer function information toinformation for each of a plurality of reference transfer functions toidentify at least one relatively close reference transfer function. 6.The method defined in claim 5 further comprising: using at least onecompensation control parameter value associated with the relativelyclose reference transfer function to control compensation circuitry. 7.The method defined in claim 1 further comprising: implementing thecompensation determined based on the generated transfer function;transmitting a further test signal having known amplitude and frequency;measuring amplitude of the further test signal as received by thereceiver; and determining whether the further test signal as received bythe receiver is under-compensated, over-compensated, or properlycompensated.
 8. The method defined in claim 7 wherein if the furthertest signal is under-compensated, then increasing the compensationimplemented in the implementing.
 9. The method defined in claim 7wherein if the further test signal is over-compensated, then decreasingthe compensation implemented in the implementing.
 10. The method definedin claim 1 further comprising: implementing the compensation determinedbased on the generated transfer function; transmitting a test datasignal having a known data eye width; measuring data eye width of thetest data signal as received by the receiver; and changing thecompensation implemented in the implementing if the data eye widthreceived by the receiver is unacceptably narrow.
 11. The method definedin claim 1 further comprising: implementing the compensation determinedbased on the generated transfer function; performing a bit error ratetest between the transmitter and the receiver; and changing thecompensation implemented in the implementing if the bit error rate testreveals an unacceptable bit error rate.
 12. A data transmission systemcomprising: transmitter circuitry; receiver circuitry; and atransmission medium for conveying a signal from the transmittercircuitry to the receiver circuitry; the transmitter circuitry includingcomponents for successively transmitting a plurality of test signalshaving known amplitudes and respective different frequencies; thereceiver circuitry including components for measuring amplitude of eachtest signal as received by the receiver circuitry; a memory for storinga plurality of values, for each test signal, indicative of whether themeasured amplitude of the test signal is greater than or less than apredetermined threshold value; a processing circuitry for providing afeedback signal to adjust the predetermined threshold value when themeasured amplitude of the test signal is less than the predeterminedthreshold value, and after the amplitude of each of the plurality oftest signals is measured: analyzing the stored plurality of values foreach test signal to identify at least one frequency where thepredetermined threshold value has been adjusted to determine thatunacceptable loss is occurring for the corresponding test signal, andgenerating a transfer function based on the stored plurality of valuesfor each test signal in response to identification of the test signalwith the frequency at which unacceptable loss is occurring; and at leastone of the transmitter and receiver circuitries including controllablecompensation components for at least partly reducing any unacceptableloss found at any of the frequencies based on the generated transferfunction after the amplitude of each of a plurality of test signals ismeasured.
 13. The system defined in claim 12 wherein the components formeasuring amplitude comprise: threshold detector circuitry for comparingthe amplitude of the test signal as received by the receiver circuitryto a plurality of different threshold levels.
 14. The system defined inclaim 12 wherein at least one of the transmitter and receivercircuitries further includes: components for at least partly determininghow the controllable compensation components should be controlled. 15.The system defined in claim 14 wherein the components for at leastpartly determining comprise: components for calculating at least onecompensation control parameter based at least in part on the amplitudesof the test signals as received by the receiver circuitry.
 16. Thesystem defined in claim 14 wherein the components for at least partlydetermining comprise: components for comparing the amplitudes of thetest signals as received by the receiver circuitry to reference valuesto select at least one compensation control parameter value that isassociated with the reference values that are relatively similar to theamplitudes.
 17. The system defined in claim 12 wherein the transmittercircuitry further includes components for transmitting a further testsignal after the controllable compensation components have beencontrolled to at least partly reduce any unacceptable loss, the furthertest signal having known amplitude and frequency; and wherein at leastone of the transmitter and receiver circuitries further includescomponents for determining whether the further test signal isunder-compensated, over-compensated, or acceptably compensated.
 18. Thesystem defined in claim 12 wherein the transmitter circuitry furtherincludes components for transmitting a test data signal having a knowndata eye width, and wherein the receiver circuitry includes componentsfor determining the data eye width of the test data signal as receivedby the receiver.
 19. The system defined in claim 12 wherein thetransmitter circuitry further includes components for transmitting aknown test data signal, and wherein the receiver circuitry includescomponents for determining a bit error rate of the test data signal asreceived by the receiver circuitry.
 20. Apparatus for enabling a systemto at least partly compensate for losses in transmission of a datasignal from transmitter programmable logic device (PLD) circuitrythrough a transmission medium to receiver programmable logic device(PLD) circuitry comprising: a communication link between the transmitterand receiver PLD circuitries; a processor circuitry associated with thereceiver PLD circuitry for selectively commanding the transmitter PLDcircuitry via the communication link to transmit a plurality ofsuccessive test signals via the transmission medium, each of the testsignals having a known amplitudes and a respective one of a plurality ofdifferent frequencies; a signal detector circuitry associated with thereceiver PLD circuitry and responsive to the processor circuitry forsubjecting each test signal received by the receiver PLD circuitry to aplurality of different amplitude level tests to determine theapproximate amplitude of each test signal as received by the receiverPLD circuitry; a memory for storing a plurality of values, for each testsignal, indicative of whether the determined approximate amplitude ofthe test signal is greater than or less than a predetermined thresholdvalue; wherein the processor circuitry provides a feedback signal thatadjusts the predetermined threshold value when the determinedapproximate amplitude of the test signal is less than the predeterminedthreshold value, and after the approximate amplitude of each of aplurality of test signals is determined: analyzes the stored pluralityof values for each test signal to identify at least one frequency wherethe predetermined threshold value has been adjusted to determine thatunacceptable loss is occurring for the corresponding test signal, andgenerates a transfer function based on the stored plurality of valuesfor each test signal in response to identification of the test signalwith the frequency at which unacceptable loss is occurring; and anequalizer circuitry associated with the receiver PLD circuitry andresponsive to the processor circuitry for equalizing the received datasignal based on an equalization characteristic and the generatedtransfer function after the approximate amplitude of each of a pluralityof test signals is determined.
 21. The apparatus defined in claim 20further comprising: memory circuitry associated with the receiver PLDcircuitry for storing information about a plurality of possible sets ofapproximate amplitudes and an equalization characteristic appropriatefor dealing with each set so that the processor circuitry can select anequalization characteristic based on comparison of the approximateamplitudes of the test signals determined by the signal detectorcircuitry to the sets.
 22. The apparatus defined in claim 20 furthercomprising: control circuitry associated with the transmitter PLDcircuitry and responsive to the processor circuitry via thecommunication link for enabling the transmitter PLD circuitry totransmit the test signals.
 23. The apparatus defined in claim 20 whereinthe communication link is adapted for communication at lower frequenciesthan the transmission medium.
 24. The apparatus defined in claim 20wherein after the equalizer circuitry has responded to the processorcircuitry, the processor circuitry is adapted to command the transmitterPLD circuitry via the communication link to transmit a further testsignal which the receiver PLD circuitry is adapted to use to testeffectiveness of the equalizer circuitry.
 25. The apparatus defined inclaim 24 wherein the further test signal is a signal of known amplitudeand frequency, and wherein the receiver PLD circuitry is adapted todetermine the amplitude of the further test signal as received by thereceiver PLD circuitry to determine the effectiveness of the equalizercircuitry.
 26. The apparatus defined in claim 24 wherein the furthertest signal is a data signal having a known data eye width, and whereinthe receiver PLD circuitry is adapted to determine the data eye width ofthe further test signal as received by the receiver PLD circuitry todetermine the effectiveness of the equalizer circuitry.
 27. Theapparatus defined in claim 24 wherein the further test signal is a knowndata signal, and wherein the receiver PLD circuitry is adapted todetermine a bit error rate of the further test signal as received by thereceiver PLD circuitry to determine the effectiveness of the equalizercircuitry.